1. Field of the Invention
This invention relates to digital computer memory systems and other data processing systems.
The invention further relates to a cycle steal and interrupt request channel including a common poll bus, and to a function integrated and shared arithmetic and logic unit processor architecture.
2. Description of the Prior Art
State of the art microprocessor designs provide three or four basic and separate functional components. First is the ROS (sometimes RAM) microinstruction address register with its incrementing, branching and linking hardware. Second is the central arithmetic and logic unit (ALU) with its associated registers and data paths. Third is the addressing and data interconnection with the main storage, that is usually treated as input/output (I/O) unit, and is architecturally combined with other system I/O devices. If the microprocessor is sophisticated enough, it will also include a fourth separate section of registers and data paths, usually defined as a channel, for performing priority nested interrupts switching, and optionally, priority multiplexed or burst mode cycle steal control (sometimes referred to as direct memory access, or DMA.)
Current microprocessors can be classified into two approaches that divide the above noted functions into a multi-chip set. The first approach allocates different functions to separate chips such as an ALU chip, a control chip, an address chip, an I/O chip, and ROS/RAM (sometimes with address control) storage chips. The second approach distributes processor functions through a number of identical chips: this approach is known as the "bit slice technique," and usually requires separate I/O control chips.
Either approach requires extensive chip interconnection, which is limited by the available I/O pins and, consequently results in duplication of logic, and also delays through the required off-chip drivers and receivers. If the data or address busses are bidirectional, no signals may be sent or received until an all off and then an all on control state is established between each chip's drivers and receivers; this causes additional delays. Also, each of these bidirectional busses require I/O pins and off chip drivers, resulting in a larger chip layout and, even worse, a higher chip power dissipation. To overcome this drawback, some architectures combine the address and data busses into one time multiplexed "Unibus," compounding further the controls and handshaking delays.
Consequently, a microprocessor architecture which minimizes the number of drivers and receivers and which can be packaged on a single chip having about 68 pin connections is needed to optimize cost and performance.
In existing computer technology, channels with up to 8 nested interrupt levels and 8 cycle steal priority levels with associated data paths, registers and buffers are extremely complex, and generally separated from the central processor on a separate chip. This is because they generally require 600 to 700 logic gates, which is nearly equivalent in logic hardware to an 8 bit microprocessor.
In accordance with this invention there is provided a microcomputer architecture including in the central processor an arithmetic and logic unit which is time shared for data processing, input/output processing, transfers of data between registers, and storage and registers, shift operations, byte manipulations, and address register modifications.
This invention further provides a microcomputer architecture including a common poll bus and control logic for enabling cycle steals and interrupt requests.
This invention further provides a plurality of stacks of working operand registers, each stack selectable by the executing interrupt level, and with absolute stack addressing by selecting the page equivalent to interrupt level.
In accordance with another aspect of this invention, there is provided, in connection with an unidirectional looped bus, address register means for addressing storage. During a portion of an execution cycle, the arithmetic and logic unit modifies the contents of the address register, the results being returned to the address register and also loaded onto the bus out for addressing storage. The invention further provides local storage register means for storing the storage address loaded on the bus out for use as a return pointer from an interrupt.
The invention still further provides, for use in a direct memory accessing (or cycle stealing) operation, local storage register means for storing indirect main storage addresses. The indirect storage address is automatically incremented, unless inhibited by the controlling I/O device, through the arithmetic and logic unit on the way to the output bus as a temporary pointer to write into main storage the data from the input/output means on bus in; or, as a temporary pointer to access main storage data for loading onto the input bus, and thence through the arithmetic and logic unit to the output bus for receipt by an input/output device.
In accordance with another aspect of the invention, particularly for use when the microprocessor of the invention is used for emulating a different computing apparatus, operand register means are provided for storing the operation code of the instruction being emulated. The arithmetic and logic unit is operated to add the operation code being emulated to the contents of the instruction address register means, the result being placed on the output bus as a displacement pointer to a table in the executable storage means, which table provides an immediate pointer to the microinstruction routine in the executable storage means for executing the operation code being emulated.
In accordance with a further aspect of the invention, a common interrupt and cycle steals polling bus means is provided. Control means, responsive to a request for an allowed interrupt, is provided for causing the change of microinstruction address pointers: the current instruction address being transferred from the address register means into the local storage register location pertaining to the current interrupt level, and the instruction address pertaining to the new interrupt level being transferred into the address register means from the local storage register accessed by the new interrupt level code.
In accordance with yet another aspect of the invention, means are provided for detecting a cycle steal request on said common poll bus. After the poll bus has been cleared of interrupt requests, the cycle steal priority is obtained from the common poll bus, and used to address the corresponding local storage register for loading into the address register means the indirect main storage address. The indirect main storage address may be incremented to either store or fetch data from the input/output device under control of the microprocessor, without requiring timing or address information from the input/output device.